(1) Field of the Invention
The present invention relates to semiconductor integrated circuits, and more specifically to semiconductor integrated circuits including on the same chip a power-ON domain as a circuit region which receives power supply from a first power source and a power-OFF domain as a circuit region which receives power supply from a second power source independent from the first power source and to which the power supply from the second power source is stopped as a result of turning-off of the second power source by control of the power-ON domain.
(2) Description of the Related Art
Conventionally known is a semiconductor integrated circuit including on the same chip a power-ON domain as a circuit region where a power is constantly ON and a power-OFF domain as a circuit region where a power is turned off when necessary. In such a semiconductor integrated circuit, upon shutoff of the power of the power-OFF domain, an unstable signal in the shut power-OFF domain may be transmitted to the constantly power-ON domain in operation.
On the contrary, suggested in Patent Document Reference (Japanese Patent Application Laid-open No. 2005-311622) is a semiconductor integrated circuit that prevents an unstable signal when a power of a power-OFF domain is shut off from being transmitted to a constantly power-ON domain in operation.
FIGS. 7A and 7B are diagrams illustrating the semiconductor integrated circuit in Patent Document 1 described above. This semiconductor integrated circuit includes: a circuit block 2 and a circuit block 3 corresponding to the constantly power-ON domain (hereinafter described as constantly power-ON circuit blocks); and a circuit block 1 corresponding to the power-OFF domain (hereinafter described as power-OFF circuit block).
As shown in FIG. 7A, in a case where powers of both the constantly power-ON circuit block and the power-OFF circuit block are ON, that is, they are in operation, by a power control signal (SWC) from the circuit block 3, power supply to the circuit block 1 is performed. At this point, a signal from the circuit block 1 can be inputted to an input circuit composed of logic gate circuits including, for example, a latch circuit FF, a NAND circuit G1, and a NOR circuit included in the circuit block 2.
On the other hand, as shown in FIG. 7B, in a case where the power of the power-OFF circuit block is turned off, that is, the power-OFF circuit block is put into a non-operating state, by the power control signal (SWC) from the circuit block 3, the power supply of the circuit block 1 is shutoff, that is, power shutoff is performed. Then by an unstable signal preventing control signal (INC) from the circuit block 3, the signal from the circuit block 1 is prevented from being inputted to the input circuit included in the circuit block 2.
By performing the power shutoff control as described above, the semiconductor integrated circuit in Patent Document 1 described above prevents the unstable signal when the power of the power-OFF circuit block is shut off from being transmitted to the constantly power-ON circuit block in operation.